The present invention relates to an integrated circuit, and more particularly, to an integrated circuit which outputs a reset signal when detecting transition of a power source voltage.
A conventional integrated circuit 31 is shown in FIG. 7, which serves as a power source detecting circuit for outputting a reset signal upon detection of a rising and a falling of a power source voltage.
As shown in the drawing, resistors R4 and R5 are connected in series between a power source line VDD and an earth line VSS, and a connection point (node N12) of these two resistors is connected to the gate of an NMOS transistor T16. The source of the NMOS transistor T16 is connected to the earth line VSS, and the drain thereof is connected to the power source line VDD through a resistor R6. Also, a connection point (node N13) of the NMOS transistor T16 and resistor R6 is connected to the gates of a PMOS transistor T17 and an NMOS transistor T18.
The source of the PMOS transistor T17 is connected to the power source line VDD, and the drain thereof is connected to the drain of the NMOS transistor T18, while the source of the NMOS transistor T18 is connected to the earth line VSS. A connection point (node N3) of the PMOS transistor T17 and NMOS transistor T18 is a reset terminal from which a reset signal is outputted.
In order to save a standby current consumption of the power source detecting circuit, the resistors employed therein are generally given with large resistance values; For example, in case of the integrated circuit 31, the resistance values of the resistors R4 and R5 are both approximately 54000 kxcexa9 and the resistance value of the resistor R6 is approximately 75000 kxcexa9.
The following will explain the operation of the integrated circuit 31 given with relatively large resistance values in cases of fast rising and slow rising power source voltages with reference to timing charts shown in FIGS. 8 and 9, respectively. In these drawings, a voltage is used as the ordinate and a time is used as the abscissa, and a broken line represents a power source voltage.
A case of the slow rising power source voltage with the rise time of longer than 1 ms will be explained first. As shown in FIG. 8, at start-up of the power source voltage, a voltage at the node N12, which shows a value of the power source voltage divided by the resistors R4 and R5, increases as the power source voltage rises. Because the NMOS transistor T16 stays OFF until the voltage at the node N12 reaches the threshold of the NMOS transistor T1, a voltage at the node N13 increases as high as the power source voltage through the resistor RG. When the voltage at the node N13 reaches the threshold of the NMOS transistor T18, the PMOS transistor T17 is switched OFF whereas the NMOS transistor T18 is switched ON, whereby a voltage at the node N3, that is, the reset signal, shifts to a low level from an initial floating state immediately after the power source supply.
Eventually, a voltage at the node N12 increases and exceeds the threshold of the NMOS transistor T16. Then, the NMOS transistor T16 is switched ON, whereby the voltage at the node N13 shifts to the low level. Accordingly, the PMOS transistor T17 is switched ON whereas the NMOS transistor T18 is switched OFF, whereby the reset signal shifts to a high level from the low level.
Then, while the power source voltage maintains a normal value, the voltage at the node N3 stays in the high level,. and when the power source voltage starts to drop, the voltage at the node N3 drops as low as the power source voltage, because the PMOS transistor T17 stays ON. When the voltage at the node N12 drops below the threshold of the NMOS transistor T16, the NMOS transistor T16 is switched OFF and the voltage at the node N13 increases as high as the power source voltage, thereby shifting to the high level. Consequently, the NMOS transistor T18 is switched ON whereas the PMOS transistor T17 is switched OFF, whereby the voltage at the node N3 shifts to the low level.
As has been discussed, in case of the slow rising power source voltage, the integrated circuit 31 detects the rising and falling of the power source voltage, and outputs a pulse of a high-level signal as a reset signal from the reset terminal (node N3) while the power source voltage maintains a predetermined value (normal period).
Next, a contrarily case of the fast rising power source voltage with the rise time of shorter than 100 As will be explained with reference to FIG. 9. As shown in the drawing, at start-up of the power source voltage, an increase of the voltage at the node N12 is delayed and gradual in comparison with the rising of the power source voltage. Thus, the voltage at the node N12 stays in the low level longer, during which an increase of the voltage at the node N13 is also delayed and gradual in comparison with the rising of the power source voltage. Throughout this period, the voltage at the node N13 keeps increasing, but remains in the low level. Then, when the voltage at the node N12 exceeds the threshold of the NMOS transistor T16, the NMOS transistor T16 is switched ON, whereupon the voltage at the node N13 starts to drop further. Accordingly, the NMOS transistor T18 stays OFF throughout the rising period of the power source voltage, while the voltage at the node N3 stays in the floating state until the PMOS transistor T17 is switched ON and then starts to increase as high as the power source voltage when the PMOS transistor T17 is switched ON.
As has been discussed, in case of the fast rising power source voltage, the reset signal has a potential as high as that of the power source voltage at start-up and starts in the high level. Thus, the integrated circuit 31 can not recognize the low level, and therefore, is unable to control the rising of the rest signal.
Generally, the power source voltage does not fall fast, and for this reason, the voltages at the nodes N12, N13, and N3 fall in the same manner as was described in case of the slow rising power source voltage. Thus, the integrated circuit 31 can control the falling of the reset signal.
Other examples of the integrated circuit which outputs a reset signal are disclosed in the following publications. Japanese Laid-open Patent Application No. 258085/1993 (Japanese Official Gazette, Tokukaihei No. 5-258085, published on Oct. 8, 1993) discloses an integrated circuit which can readily output a reset signal in case of either fast or slow rising power source voltage. Japanese Laid-open Patent Application No. 283997/1993 (Japanese Official Gazette, Tokukaihei No. 5-283997, published on Oct. 29, 1993) discloses an integrated circuit having a high voltage source and a low voltage source, so that a malfunction of a circuit operating on a high voltage source is prevented when a voltage in the low voltage source drops. Japanese Laidopen Patent Application No. 326825/1993 (Japanese Official Gazette, Tokukaihei No. 5-326825, published on Dec. 10, 1993) discloses an integrated circuit which stops supply of the power source when the power source voltage drops to or below a predetermined value, so that damages caused by external noise is prevented. Japanese Laid-open Patent Application No. 118019/1986 (Japanese Official Gazette, Tokukaisho No. 61-118019, published on Jun. 5, 1986) discloses an integrated circuit which secures clearing job stability by setting a clearing time for an internal circuit after detecting that the power source voltage has reached the operable lower limit voltage of the internal circuit.
As has been discussed, the conventional integrated circuit 31 can not control the rising of the reset signal in case of the fast rising power source voltage. Thus, a circuit which is to be reset by the integrated circuit 31 may not be initialized properly. Smaller values may be given to the resistors R4, R5, and R6, so that the reset operation is performed properly in response to the power source voltage at any rising rate. However, in this case, there is a problem that a standby current consumption (a current flowing from the power source line VDD to the earth line VSS through the resistors R4 and R5, and a current flowing from the power source line VDD to the earth line VSS through the resistor R6 and NMOS transistor T16) of the integrated circuit 31 increases undesirably while the circuit to be reset is on standby, that is, while it is ready to accept commands, such as signal reading, writing, erasing, etc.
In case of the integrated circuit of Japanese Laid-open Patent Application No. 258085/1993 supra, a reset signal can be generated properly also in case of the fast rising power source voltage, but it can not control the standby current consumption. Further, the integrated circuits in the rest of the foregoing publications do not concern a problem arising from the rising rate of the power source voltage.
It is therefore an object of the present invention to provide an integrated circuit which can save the standby current consumption and output a reset signal properly in response to the power source voltage at any rising rate.
In order to fulfill the above and other objects, an integrated circuit of the present invention for generating a reset signal in a normal period during which a power source voltage maintains a predetermined threshold is furnished with: first and second power source voltage detecting circuits for detecting whether the power source voltage reaches the threshold or not, each having a different operation rate and different power consumption; and a reset signal generating circuit for generating the reset signal based on detection results from the first and second power source voltage detecting circuits, the second power source voltage detecting circuit having a higher operation rate being furnished with a cutting circuit for cutting a current flowing therein when the first power source voltage detecting circuit having smaller power consumption detects that the power source voltage reaches the threshold. The cutting circuit may cut the current either partially or entirely. It should be appreciated, however, that the more the current is cut, the more the power consumption of the integrated circuit is saved.
According to the above arrangement, because the operation rate of the second power source voltage detecting circuit is set high, even when the power source voltage rises fast, the reset signal can be generated without causing any conventional problem that the reset signal has a potential as high as the power source voltage and starts in the high level. Further, after the first power source voltage detecting circuit having a smaller current consumption detects the rising of the power source voltage, the current flowing in the second power source voltage detecting circuit is cut by the cutting circuit, and the reset signal generating circuit generates the reset signal based on the detection result from the first power source voltage detecting circuit. Consequently, the current consumption is saved considerably compared with a case where the second power source voltage detecting circuit keeps operating on one hand, and on the other hand, the falling of the power source voltage which happens gradually in comparison with the rising can be detected in a secure manner. Thus, an integrated circuit which can save the standby current consumption and at the same time output the reset signal properly in response to the power source voltage at any rising rate can be provided.
It is preferable that the integrated circuit is further arranged in such a manner that: each of the first and second power source voltage detecting circuits is furnished with a resistor and a detecting circuit, the resistor being provided on a DC path starting from a first power source line to which the power source voltage is supplied and ending at a second power source line kept at a predetermined potential lower than the power source voltage, the detecting circuit detecting whether the power source voltage reaches the threshold based on a potential at one end of the resistor serving as a first node; a resistance value of the resistor provided to the second power source voltage detecting circuit is set smaller than a resistance value of the resistor provided to the first power source voltage detecting circuit; and the cutting circuit is a switch provided on the DC path in the second power source voltage detecting circuit.
According to the above arrangement, a smaller resistance value is given to the resistor in the second power source voltage detecting circuit compared with that in the first power source voltage detecting circuit. Hence, power consumption of the first power source voltage detecting circuit can be readily set smaller than that of the second power source voltage detecting circuit. In addition, the operation rate of the second power source voltage detecting circuit can be set higher than that of the first power source voltage detecting circuit. Further, after the first power source voltage detecting circuit detects that the power source voltage reaches the threshold, the DC path in the second power source voltage detecting circuit is cut, in which a larger current flows compared with the DC path in the first power source voltage detecting circuit, thereby saving the power consumption of the integrated circuit considerably. Consequently, an integrated circuit which can save the standby current consumption and at the same time output the reset signal properly in response to the power source voltage at any rising rate can be provided.
It is preferable that the integrated circuit is further arranged in such a manner that: the second power source voltage detecting circuit maintains an output at a level at the instant the current is cut while the current is kept cut; and the reset signal generating circuit includes a logical circuit which maintains the reset signal at a first level indicating the normal period when both of the first and second power source voltage detecting circuits detect that the power source voltage reaches the threshold. The above arrangement makes it possible to assemble the reset signal generating circuit with a basic logical circuit.
In each of the above arrangements, once the first power source voltage detecting circuit detects that the power source voltage reaches the threshold, the power consumption can be saved for any cutting period during which the current is kept cut by the cutting circuit. It should be appreciated, however, that the longer the cutting period, the more the power consumption can be saved.
It is preferable that the integrated circuit is further arranged in such a manner that the cutting circuit cuts the current when the reset signal indicates the normal period. According to the above arrangement, the current flowing in the second power source voltage detecting circuit is cut while the reset signal is maintained by the first power source voltage detecting circuit, whereby the power consumption can be saved more compared with a case where the current is cut for a segment in the normal period.
Also, in addition to the arrangement of the resistor, the integrated circuit may be arranged in such a manner that: the detecting circuit of the second power source voltage detecting circuit detects that the power source voltage reaches the threshold when a potential at the first node shifts to a low level from a high level, and wherein the second power source voltage detecting circuit is further furnished with: a first switching element which is provided between a lower potential end of the resistor serving as the first node and the second power source line and conducts when the power source voltage is applied to a control terminal and reaches a predetermined switching ON level; a capacitor provided between the low potential end of the resistor and the first power source line; and a second switching element provided between a high potential end of the resistor and the first power source line.
In the above arrangement, the first switching element keeps conducting until the power source voltage reaches the switching ON level. Under these conditions, even if the second switching element is cut, the potential at the first node is as high as the power source voltage through the capacitor. Thus, the potential at the first node can be set to the high level immediately before the power source voltage reaches the switching ON level.
Further, when the power source voltage reaches the switching ON level, the first switching element shifts to the conducting state. Under these conditions, the power source voltage has reached the switching ON level, and therefore, the second switching element conducts without causing any problem. Consequently, the potential at the first node drops as low as the potential of the second power source line and shifts to the low level. Thus, the detecting circuit can detect that the power source voltage reaches the threshold even in case of the fast rising power source voltage.
Under these conditions, even if the second switching element serving as the switch is cut, the first node stays in the low level because the first switching element is conducting. Consequently, the second power source voltage detecting circuit can maintain the output at the value at the instant the power source voltage reaches the threshold even if the second switching element is cut.
As another preferable embodiment, in addition to the arrangement of the resistor, the integrated circuit may be arranged in such a manner that: the detecting circuit of the second power source voltage detecting circuit is furnished with a detecting unit which detects that the power source voltage reaches the threshold when a potential at a second node shifts to a low level from a high level; a serial resistor connected to the first power source line at one end; a first switching element which is provided between the other end of the serial resistor and the second node and conducts when a potential at the second node reaches a predetermined switching ON level; and a second switching element which is provided between the second node and the second power source line and conducts when a potential at the first node reaches a predetermined switching ON level, and wherein the second power source voltage detecting circuit is further furnished with: a third switching element which is provided between a high potential end of the resistor serving as the first node and the first power source line, connected to the first node at a control terminal, and conducts when the power source voltage reaches a predetermined switching ON level; a fourth switching element which is provided between a low potential end of the resistor and the second power source line as the switch and conducts while the reset signal is generated; a fifth switching element which is provided between the first node and the first power source line and kept cut while the reset signal is generated; and a capacitor provided between the first node and the second power source line.
According to the above arrangement, the potential at the first node is as low as the potential of the second power source line through the capacitor when the power source is supplied. Because the first through fifth switching elements are in the cutting state at this point, the potential at the first node increases by the parasitic capacity of the first switching element as the power source voltage applied to the first power source line rises. As the power source voltage rises further and reaches the switching ON level of the first and third switching elements, the first and third switching elements start to conduct, whereby the potential at the first node and the potential at the second node start to increase. Consequently, the potential at the second node keeps increasing until the second switching element starts to conduct. Thus, the potential at the second node can be set to the high level immediately before the second switching element starts to conduct.
On the other hand, when the potential at the second node reaches the switching ON level of the second switching element and the second switching element starts to conduct, the potential at the second node starts to drop gradually, because it is connected to the second power source line through the second switching element. When the power source voltage exceeds the predetermined value, the potential at the second node drops further and shifts to the low level. Consequently, the detecting unit can generate the reset signal even in case of the fast rising power source voltage.
Under these conditions, even if the fourth switching element serving as the switch is cut, the second node is maintained at the high level and the first node is maintained at the low level, because the fifth switching element is conducting. Thus, even if the fourth switching element is cut, the second power source voltage detecting circuit can maintain the output at the value at the instant the power source voltage reaches the threshold.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.